In the process of fabricating a semiconductor device, one important step is interfacing peripheral devices with the various active devices and interconnects defined in the semiconductor substrate. Normally, the active devices are first formed in a silicon substrate and then a protective oxide layer placed thereover. Access openings or via's are then patterned in the thick oxide layer followed by formation of metal contact pads. This conventional method is acceptable for geometries wherein the thickness of the oxide is considerably less than the width of the access openings. However, with decreasing geometries, the size of access openings is rapidly approaching the thickness of the protective oxide and present fabrication methods are found to be insufficient.
Present plasma technology approaches its limit for devices in which the protective oxide is greater than 5000 .ANG. with contact spacings having geometries of less than four microns from edge to edge. When this conventional technology is utilized for geometries of this scale, definition around the edges of the contact holes is poorly defined, resulting in high resistance contacts or defective contacts that may present future reliability problems.
In view of the above disadvantages, there exists a need for a method of forming contacts that is acceptable with the type of geometries encountered with VLSI circuits.